This invention relates to a parallel analog-to-digital converter circuit which has an erroneous-operation detecting function and which is suitable for embodiment of semiconductor integrated circuit.
When it is desired to convert an analog signal, such as video signal or the like having a relatively high frequency, into a digital signal, a high speed analog-to-digital converter (hereinafter referred to as an A/D converter) is used.
FIG. 1 is a view showing the construction of a prior art parallel A/D converter circuit suitable for subjecting an analog signal such as a video signal or the like having a high frequency to A/D conversion. In this A/D converter circuit, between a point of applying a reference voltage +V.sub.REF of positive polarity and a point of applying a reference voltage -V.sub.REF of negative polarity, a plurality of resistors I are connected in series, and so a different reference level signal is obtained from the point of serial connection between each pair of any two adjacent resistors I. The reference level signal is supplied, jointly with the analog signal IN, to each of a plurality of level comparator circuits 10.sub.1 to 10.sub.i, each consisting of an autozero type comparator, in which the analog input signal level and the reference level signal are compared with each other on a parallel basis.
For purposes of illustration let us take the level comparator circuit 10.sub.2 as an example. An analog switch 11 is first set to the "on" state by a pair of clock pulses .phi..sub.1 and .phi..sub.2, with the result that short-circuiting occurs between the input and output ends of an inverter 12. Thus, the operating point of this inverter is determined. At the same time, an analog switch 13, which is supplied at its input end with a reference level signal, is also set to the "on" state by the same pair of clock pulses .phi..sub.1 and .phi..sub.2, whereby the reference level signal is supplied to one end of a coupling capacitor 14. At this time, the level at one end of the coupling capacitor 14 is set to the reference level while the level at the other end of this coupling capacitor is set to the level at the operating point of the inverter 12, for example, the level equal to one half of the level of a power source voltage supplied to the inverter 12. At the next time sequence, another analog switch 15 is set to the "on" state by a pair of clock pulses .phi..sub.3 and .phi..sub.4, with the result that the analog input signal level is supplied to one end of the coupling capacitor 14. At this time, the level at the other end of the coupling capacitor becomes equal to a level which is deviated by the difference between the reference level and the analog input signal level from the level at the operating point of the inverter 12. And the level corresponding to this deviation is inverted and amplified by the inverter 12. The output of the inverter 12 is subjected to a shaping of the waveform by another inverter 16, and from this inverter 16 the result of the comparison between the reference level and the analog input signal level is outputted as a digital value of "1" level or "0" level. Another analog switch 17 is next set to the "on" state by another pair of clock pulses .phi..sub.5 and .phi..sub.6, whereby said result of comparison is supplied to the input end of an inverter 18 in which the level thereof is inverted. Next, during the period of inversion of the paired clock pulses .phi..sub.5 and .phi..sub.6, a clocked inverter 19 connected to the inverter 18 in the form of an antiparallel connection is rendered operative. Thus, the output of the inverter 18 is inverted by this clocked inverter 19 and is fed back to the input end of the inverter 18. Accordingly, the result of comparison supplied to the inverter 18 through the analog switch 17 is stable held, during the one-bit period of the clock pulses .phi..sub.5 and .phi..sub.6, by a stabilizer circuit 20 comprised of the inverter 18 and the clocked inverter 19.
In the level comparator circuit 10 which is supplied with the reference level higher than the analog input signal level, the input signal level of the inverter 12 after the analog switch 15 is turned "on" becomes lower than the level at the operating point of that inverter, with the result that the output of the inverter 16 becomes "0" level, while the output of the stabilizer circuit 20 becomes "1" level. On the other hand, the output of the stabilizer circuit 20 in the level comparator circuit 10 supplied with reference level lower than the analog input signal level becomes "0" level. In this way, in said plurality of level comparator circuits 10.sub.1 to 10.sub.i, the reference signals of different levels are compared in level with the analog input signal on a parallel basis. Thus, the outputs of the level comparator circuits supplied with the reference levels higher than the analog input signal level all become "1" level, while the outputs of the level comparator circuits supplied with the reference levels lower than the analog input signal level all become "0" level.
The outputs of the above-mentioned level comparator circuits 10.sub.1 to 10.sub.i are supplied to a digital signal generator circuit 30. This circuit 30 is a circuit which, in accordance with the output of the level comparator circuits 10.sub.1 to 10.sub.i, generates a digital signal of a plurality of bits corresponding to the analog input signal level. In FIG. 1, a digital signal generator circuit which generates a digital signal of 6 bits is shown. In this case, 64-level comparator circuits 10 are necessary. (that is, i=64.)
In the digital signal generator circuit 30, the outputs from the level comparator circuits 10.sub.1 to 10.sub.i are respectively inverted by a plurality of inverters 31.sub.1 to 31.sub.i, the outputs of which are supplied to a plurality of NAND gates 32.sub.1 to 32.sub.i at one input end thereof. The NAND gate 32.sub.1, which receives at one input end the output of the inverter 31.sub.1 for inverting the output of the level comparator circuit 10.sub.1 supplied with the highest reference level, is constantly supplied at the other input end with a power source voltage of positive polarity. Further, the outputs from the level comparator circuits 10.sub.1 to 10.sub.i-1, which are supplied with the reference levels adjacent to, but higher than, the reference levels supplied to the level comparator circuits 10.sub.2 to 10.sub.i, are directly supplied to the other input ends of the NAND gates 32.sub.2 to 32.sub.i. Further, the output of the level comparator circuit 10.sub.i supplied with the lowest reference level is supplied to one input end of a separate NAND gate 32.sub.i+1, which is supplied at its other input end with the output of an inverter 31.sub.i+1 which is supplied with a ground voltage at all times.
The circuit consisting of one of the inverters 31.sub.1 to 31.sub.i and a corresponding one of the NAND gates 32.sub.1 to 32.sub.i is intended to detect whether or not the output levels of a corresponding level comparator circuit set consisting of two level comparator circuits 10.sub.1 and 10.sub.2, 10.sub.2 and 10.sub.3, . . . or 10.sub.i-1 and 10.sub.i, respectively supplied with two adjacent reference levels, differ from each other. Where the output levels of two such level comparator circuits are equal to each other, the output of the corresponding NAND gate 32 becomes "1" level. Where those output levels differ from each other, the output of the corresponding NAND gate 32 becomes "0" level. Further, since the NAND gate 32.sub.1 is supplied, through the inverter 31.sub.1, with the output of the level comparator circuit 10.sub.1 and also supplied with a "1" level signal, this inverter 31.sub.1 and NAND gate 32.sub.1 constitute a detection circuit for detecting whether or not the output of a level comparator circuit, supplied with a reference level at all times higher than the analog input signal level, differs from the output of the level comparator circuit 10.sub.1. The output from the level comparator circuit 10.sub.1 is supplied through the inverter 31.sub.1 to one input terminal of the NAND gate 32.sub.1. A "1" level signal is supplied to the input terminal of the NAND gate 32.sub.1 at all times. Hence, the inverter 31.sub.1 and the NAND gate 32.sub.1 from a level comparator circuit which receives a reference level higher than the highest level that an analog input signal has which may be converted into a digital signal. The outputs of the NAND gates 32.sub.1 to 32.sub.i+1 are supplied to a plurality of control lines 33.sub.1 to 33.sub.i arranged in a specified direction, respectively, and are inverted by a plurality of inverters 34.sub.1 to 34.sub.i+1, respectively. The outputs of the inverters 34.sub.1 to 34.sub.i+1 are supplied to a plurality of control lines 35.sub.1 to 35.sub.i+1 arranged in the same direction as the control lines 33.sub.1 to 33.sub.i+1, respectively. Six output lines 36 to 41 are so provided as to intersect the control lines 33.sub.1 to 33.sub.i and 35.sub.1 to 35.sub.i+1. Between these output lines 36 to 41 and the point of application of the power source voltage or the point of ground potential, there are connected P channel MOS transistors 43 and N channel MOS transistors 42 whose gates are supplied selectively with the signals of the control lines 33.sub.1 to 33.sub.i and 35.sub.1 to 35.sub.i+1, respectively. The MOS transistors 42 and the MOS transistors 43 are arranged in the form of a specified bit pattern, thereby constituting a programmable logic array (PLA). When these MOS transistors are selectively set to the "on" state in accordance with the signals of the control lines 33.sub.1 to 33.sub.i and 35.sub.1 to 35.sub.i+1, a digital signal of six bits corresponding to the analog input signal IN is outputted from said six output lines 36 to 41. Further, an overflow line 44, which is set at "1" level when said analog input signal level is higher than the reference level supplied to the level comparator circuit 10.sub.1, is connected to the output end of the inverter 34.sub.1.
That is to say, in the A/D converter circuit having the foregoing construction, when the A/D converting operation is carried out once, all of the outputs of the level comparator circuits 10 supplied with the reference level higher than the analog input signal level become "1" level, and all of the outputs of the level comparator circuits 10 supplied with the reference level lower than the analog input signal level become "0" level. And the output level of the level comparator circuit or circuits whose outputs are varied from "1" level to "0" level are detected by the inverters 31.sub.1 to 31.sub.i+1 and the NAND gates 32.sub.1 to 32.sub.i+1 of the digital signal generator circuit 30. In accordance with the results of detection, the MOS transistors 42 and 43 operate selectively, thereby obtaining a digital signal.
In the prior art parallel A/D converter circuit having the foregoing construction, when the frequency of the clock pulses .phi..sub.1 to .phi..sub.6 for controlling the level comparator circuits 10.sub.1 to 10.sub.i is increased by degrees, it is possible to increase the speed of A/D conversion. However, when the frequency of the clock pulses .phi..sub.1 to .phi..sub.6 is increased so highly that the operation speed of the level comparator circuits 10.sub.1 to 10.sub.i reaches a critical operation limit, some of the level comparator circuits 10 will operate erroneously. The digital signal obtained at this time becomes inaccurate and, in addition, when this circuit is fabricated in an integrated circuit, the said critical operation limit varies due to the process of manufacture. For this fact, it is necessary to sort the manufactured integrated circuits so as to be guaranteed commerically to have a specified converting speed by measuring the upper limit speed of the respective circuits. In the prior art circuit, however, no signal is outputted which enables direct determination of whether or not there exists a level comparator circuit 10 performing erroneous operation. This necessitates making such a judgement by means of said digital signal of six bits.
Since high speed analog processing apparatus is required for making such a judgement by the said digital signal, the cost for the said sorting operation increases, which significantly increases the manufacturing cost of the circuit.
Further, since a high speed signal is used in performing the above-mentioned sorting operation by the use of the high speed analog processing apparatus, the presence of even a small capacitance would cause a delay in that high speed signal, thus failing to make a precise judgement. Actually, in performing the said sorting operation, it is necessary to connect a measuring lead to an electrode on the wafer or to conduct mutual wiring between the wafer and the analog processing apparatus. This causes the production of a stray capacitance. In the prior art circuit, therefore, it is impossible to measure the upper limit speed of each integrated circuit while it is in the form of a wafer.
Further, even after the circuit is made into a product, it is necessary to judge whether or not each level comparator circuit 10.sub.1 . . . or 10.sub.i performs an erroneous operation, and this judgement cannot be easily made for the above-mentioned reasons.